Senior Hardware Engineer - Palo Alto
Role: Sr. Physical Design Engineer
As a Sr. physical design engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block and subchip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to drive the overall Physical Design aspects, leading to a successful tapeout and production silicon.
Key Qualifications include (but not limited to): Extensive physical design experiences at both the block level and subchip level, as well as full-chip level is a plus.
Deep knowledge in physical design, including physical aware synthesis, floorplanning, clock tree implementation, routing, STA timing signoff, and chip-finishing.Good knowledge of basic soc architecture. Be able to work with Front-end design team to address timing, congestion and power issues.
In-Depth Knowledge of design flow from RTL to GDSII.
Good knowledge of EM-IR sign-off requirements.
Experience in using EDA tools like Synopsys (/Cadence) for PPA optimization.
Good script skills such as perl/tcl.
Responsibilities include (but not limited to): Perform subchip level and block level place and route, and close design to meeting performance, power and area.
Lead and Perform all aspects of full chip SoC integration activities: die size optimization, floorplanning, hard IP integration, partitioning, chip level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing, DFT strategy planning, and final physical verification.
Good knowledge of timing analysis, power analysis, physical verification (DRC/LVS), and formal verification
Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation.Define EM-IR signoff requirements and sign-off methodology.
Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis
Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on-
die model for package & die co-design analysis
Be an EM-IR sign-off lead with successful tape out track records
Excellent hand-on experience in voltage drop analysis using redhawk or redhawk-SC
Excellent hand-on experience and debugging skills of finding root cause of voltage drop
and EM issues
Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to
detail
Work closely with the Foundry Engineer and Microarchitecture team to establish logic levels, Multi-Vt library mixes and choices of tracks, metal-stackup, etc.Define flows through various EDA tools and write scripts for automation for floor planning, placement, routing, crosstalk avoidance, judicious usage of cell libraries and physical verification
Work with the Microarchitecture, Signal Integrity, Power Integrity and Thermal team to ensure that the floorplan and the logic is designed in such a way such that the Substrate/Packaging and Board Layout and the Power Delivery comprehend the power domains, multiple voltages, power integrity requirements, power gating, specify power sequencing to eliminate leakage paths, always-on power, minimize hot-spots, etc.
Design the floorplan to ensure that the power distribution for the chip for the various voltage domains is consistent with the bump and bump-ball map to ensure power integrity (i.e., minimize voltage droop, utilization of local LDOs) and signal integrity (e.g., aggressor nets)
Ensure that the clocking architecture is robust and meets the timing requirements - i.e., well versed in Clock Tree Synthesis, Static Timing Analysis, Timing closure methodologies, Clock gating, reference clocks, PLL placement, clock muxing, etc.
Well versed in parasitic extraction, LVS/DRC and other verification checks - Physical, Power, Post-Layout Timing