Senior IC Layout Design Engineer / Team Lead
Chelsea Search Group Dallas
Senior IC Layout Design Engineer/Team Lead
Dallas, Texas (onsite / hybrid)
Full-time/Direct-hire + Benefits
Chip level integration including IP blocks, digital blocks, and analog blocks
Chip level verification including DRC/LVS/EMIR, parasitic extraction, and metal density fill
Attention to details, reading layout specifications
Bachelors degree in electrical engineering or associates degree in Layout
Experience in LVS and DRC
Solid experience in Cadence Virtuoso/Synopsys Custom Compiler Layout tool and verification tools, Calibre/PVS/IC Validator
Dallas, Texas (onsite / hybrid)
Full-time/Direct-hire + Benefits
US Citizen or US Permanent Resident
Responsibilities: Leading a layout team working on mixed-signal chips and memory chips (ROIC)
Chip level floor planning of chips including pad frame, array architecture, power bussingChip level integration including IP blocks, digital blocks, and analog blocks
Chip level verification including DRC/LVS/EMIR, parasitic extraction, and metal density fill
Effective collaboration with local and remote team members
Requirements: 10+ years industry experience in IC layout
Ability to work under time constraintsAttention to details, reading layout specifications
Bachelors degree in electrical engineering or associates degree in Layout
Experience in LVS and DRC
Good understanding of the semiconductor foundry process flow
Layout experience with memory blocks, e.g. sense amplifiers and pitch constrained row/column decoders; custom digital logic, analog blocks including bandgap, regulators, PLL, high-speed SerDesSolid experience in Cadence Virtuoso/Synopsys Custom Compiler Layout tool and verification tools, Calibre/PVS/IC Validator
Strong communication and customer service skills
Javier LeonFJLrecruiter @ (link removed)
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