High Speed Analog Mixed Signal Physical Design Engineer

Design goals also include low-power analog designs to address our low-power wireless products. The primary responsibility of this position entails working within a team to deliver analog and mixed-signal transistor level circuit designs along with the physical layouts of the high speed circuits for high-speed, low-power PHY SerDes blocks.

Minimum Qualifications:

Master's Degree plus 3-15 years of analog design experience - or - PhD with analog design experience up to 10 years of experience plus:

• Experience in designing op-amps, LDOs, VCO, PLL, DLL, High Speed Clock Distribution, Charge pump, Linear Equalizer
• Experience in using SPICE simulators (Cadence Analog Artist experience is preferred).
• Experience using schematic capture tools (Virtuoso preferred).
• Signal integrity in high speed wireline design
• automate circuit design and verification work
• Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off

Preferred Qualifications:

Understanding of FinFet CMOS process effects on designs and layout

Education:

Master's Degree plus 3-15 years of analog design experience - or - PhD with analog design internship experience up to 10 years of experience plus

Duration: 1 year+