Sr. Verification Engineer
Paradigm Works is working with its client on the development of large, high-performance ASICs and chip sets.
We seek a talented Senior Verification Engineer for Regular Employment OR Contract Employment to fill a critical role developing and enhancing SystemVerilog UVM, testbenches for CPU/CPU chips and ship sets for graphics applications.
Requirements:- 5+ years relevant experience verifying ASICs and FPGAs.
- 1-2 projects creating and utilizing System Verilog UVM test benches.
- 1-2 projects verifying Memory Subsystems and cache based systems including but not limited to MMU (Memory Management Unit), Page Tables, and Cache Coherency protocols.
- UNIX scripting experience (TCL, Perl, Python).
- Functional coverage experience a plus.
- Experience with System Verilog OVM and VMM a plus.
- Specman'e experience a plus.
- C, C++, System C, and Object Oriented Programming experience a plus.
Education Requirements: BSEE, BSCS, or equivalent experience in closely related field.
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